The present invention relates to integrated circuit fabrication methods and structures, and particularly to integrated circuits with minimum linewidths below one-half micron.
Background: Planarization
As the degree of integration has advanced, it has become increasingly apparently that it is desirable to minimize the topographical excursion of the surface at each level, especially the upper levels. To accomplish this, various planarization schemes have been used to planarize the inter-level dielectric. Some of these include Chemical-Mechanical-Polishing (CMP), use of Permanent Spin-on-glass (left in place in the final chip), and Sacrificial Etchback Spin-on-glass (SOG).
Spin-on glass deposition is an example of a “sol-gel” process, which has been used in the semiconductor industry for many years. The unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally, e.g., Dauksher et al., “Three ‘low Dt’ options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process,” 139 J.ELECTROCHEM.SOC. 532-536 (1992), which is hereby incorporated by reference.
Background: SRAM Cell Operation
One of the two most common types of SRAM cell is the “4-T” cell, which uses resistive loads. FIG. 7 is a circuit diagram of such a cell (a 4-transistor 2-resistor MOS SRAM cell). In the example shown, the numbering of the bitlines and wordlines indicates that this cell would be in the n-th row and m-th column of an array (or subarray) of memory cells. In this cell, NMOS driver transistors D1 and D2, loaded by resistors R1 and R2, are cross-connected to form a latch. Pass transistors PT1 and PT2 are both accessed by a respective wordline WLn, to connect the two complementary nodes of the latch to a respective complementary pair of bitlines BLm and BLm* when wordline WLn goes high. Thus, in read mode, when wordline WLn goes high, whichever one of the driver transistors (D1 or D2) is ON will pull down one of the bitlines (BLm or BLm*), producing a data signal which can be read. In write mode, the bitlines will be clamped by strong drivers, and the pass transistors PT1 and PT2 will pass enough current to change the state of the latch to correspond to the bitline voltages.
In such a memory cell, the resistors R1 and R2 must pass enough current to offset the leakage currents which tend to discharge the high node of the latch. These resistors are conventionally made from nearly intrinsic polysilicon, and therefore tend to have very high resistance values (which may range from many gigaohms up to teraohms). Unfortunately, the resistivity of such polysilicon is fairly variable, and an excessive value for the resistors may cause the cell to lose data under high-temperature conditions. An excessively low value for the polysilicon resistor may lead to excess static power consumption. Thus, precise control of the resistor values would be highly desirable.
Innovative SRAM Structure and Process
This disclosure describes an improved method of four transistor SRAM cell fabrication, wherein planarization is performed before metal formation (and actually before resistor formation). The pre-metal planarization utilizes a sandwich structure comprising permanent SOG, undoped glass, and permanent SOG. The undoped glass is used as a buffer layer between two layers of spin-on-glass to prevent SOG cracks. The double SOG spin enhances the degree of planarization.
The disclosed inventions thus provide the advantages of reduced topography at the poly-2 level, and hence more accurate patterning of the poly resistors, and hence a reduced poly-R resistance value by shortening resistor length (less surface contour due to better planarity). This provides more precise manufacturing control which can be used to set speed and power more reliably.